The Phase Locked Loops (PLLs) in general, and a special class of PLLs known as Clock Synthesizer Units (CSUs), require Voltage Controlled Oscillators (VCOs) to generate an output clock signal, where the frequency of the output clock signal is proportional to an input control voltage. The VCO must start-up reliably in order to guarantee CSU stability in the steady-state. Failure of the VCO to start-up reliably will result in a non-functional PLL/CSU.
One known method of implementing a VCO is the complementary cross-coupled LC-oscillator, described by Craninckx et al, in, “A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), May 1997, pp. 403-406. A phase noise analysis of this type of VCO was carried out by Hajimiri et al. in, “Design Issues in CMOS Differential LC Oscillators,” in J. Solid-State Circuits, Vol. 34, No. 5, May 1999, pp. 717-724. Hajimiri et al. showed that this type of oscillator offers a number of advantages over NMOS-only or PMOS-only structures, including: higher transconductance (gm) for a given current and therefore faster switching, and better rise- and fall-time symmetry resulting in a smaller 1/f3 flicker phase noise with lower flicker corner frequency. Given these advantages, the VCO core described in the above papers is used for the present invention, though it should be noted that the invention could be used with other architectures.
FIG. 1 is a diagram showing the architecture of an example of a well known complementary cross-coupled LC VCO 10, as described in the references above. The example VCO 10 includes a cross-coupled pair of PMOS transistors 11 and 12, and a cross-coupled pair of NMOS transistors 13 and 14. The cross-coupled transistor devices 11, 12, 13 and 14 set the common mode voltage, VCM=(V++V−)/2. Ideally, the devices are well matched and common mode voltage is equivalent to half the supply voltage (i.e. VCM=VDD/2 in FIG. 1). Frequency selectivity is provided by a fixed inductor (L) 15 and a variable capacitor (C) 16, where the capacitor is controlled using analog voltage and/or digital selection. The inductor 15 and capacitor 16 are sometimes referred to as the “LC tank”.
The gain of cross-coupled devices 11-14 must be sufficiently large to guarantee start-up of the VCO. Gain is dependent on device transconductance, which in turn is proportional to device width (W) and gate overdrive-voltage, where overdrive-voltage is the voltage between gate and source in excess of the transistor threshold (turn-on) voltage. Once steady-state has been reached in the LC VCO, only a small amount of energy need be injected each cycle to compensate for tank losses.
In low-voltage deep submicron CMOS technologies, circuit power reduction is often achieved by reducing supply voltage. In traditional CMOS technology scaling, the reduction in power supply voltage is assumed to be accompanied by a reduction in device threshold voltage. More recently, however, when device feature sizes (mainly minimum channel length Lmin) shrink in each new generation of CMOS technology the device threshold voltages may be held steady or increased slightly to further reduce power drawn from the supply, reduce power wasted by drain-source leakage in the off-state, and improve digital circuit noise margin. As a consequence, the supply voltage for a complementary cross-coupled VCO will have a lower limit determined by the fact that the common mode voltage across balanced complementary PMOS or NMOS pairs must be at least equal to the corresponding transistor threshold voltage(s) to avoid significant reductions in device transconductance, and in turn decreases in regenerative loop gain in a VCO such that the gain is no longer sufficient to guarantee the oscillation start-up.
To overcome this limitation, alternative VCO architectures may be used. For example, an NMOS-only (or PMOS-only) VCO structure does not require a half-supply common mode voltage, offering more flexibility in design. However, the use of this type of VCO means the advantages listed above for the complementary cross-coupled structure are lost. Moreover, the remaining NMOS (or PMOS) transistors in the circuit can be subject to electrical over-stress (EOS) of voltage, a condition that will degrade long-term reliability and lifetime of the device.
Transconductance can be increased somewhat by increasing device width (W), but the impact of increasing width is diminished when common mode voltage across PMOS or NMOS pair is less than the corresponding transistor threshold voltage, as devices in this case will be biased in the sub-threshold regime. At the same time, increasing width adds additional capacitive parasitics to the VCO tank, thereby reducing frequency tuning range and/or reducing maximum oscillating frequency of the VCO.
The inventors have determined a need for methods and apparatus for increasing the robustness of oscillation start-up reliability without impacting VCO frequency tuning range and in which the advantages of the cross-coupled VCO are retained.